//-------------------------------------------------
//  Title: test_control.v
//  Module: test_control
//  Function: Test Bench for control.v
//  Coder: Mitchell Kline
//  Date Created: Apr 5, 2007
//-------------------------------------------------

module test_control;

  reg [31:0] IW;

  wire [6:0] Control;
  wire [3:0] Op;

  control C1(
    .RegDest(Control[6]),
    .ALUSrc(Control[5]),
    .MemtoReg(Control[4]),
    .RegWrite(Control[3]),    
    .MemRead(Control[2]),
    .MemWrite(Control[1]),
    .Branch(Control[0]),
    .IW(IW),
    .ALUOp(Op)
  );

  initial begin
    $display("\t\ttime,\tIW[31:26],\t\IW[5:0],\tOp,\tControl");
    $monitor("%d,\t%d,\t\t%d,\t\t%b,\t%b",$time,IW[31:26],IW[5:0],Op,Control);
  end

  initial begin
    #1  IW <= {`RTYPE,20'd0,6'd32};
    #20 $finish;
  end

endmodule

